1. Field of the Invention
The present invention relates to a power transistor circuit and the method thereof, and more particularly, to a power transistor circuit that has a high voltage limit and a low inner resistance.
2. Description of the Related Art
FIG. 1 is a hint diagram of a prior art photoflash capacitor charger, where the inductor 12 in the first winding side has its voltage drop and current conductance controlled by a power transistor 11. The power transistor 11 acts as a switch. As far as the process of the double-diffused metal oxide semiconductor (DMOS) is concerned, it provides a low inner resistance, good conductance speed and lower power consumption. However, the power transistor made from the DMOS has a voltage limit of is only 30 volts, which does not satisfy the requirement of 40-volt voltage limit for the photoflash capacitor charger. In other words, the prior DMOS technique based on the BCD process suffers from a reliability issue when the output voltage is greater than 30 volts, let alone the high voltage of 40 volts.
Another prior method to solve this problem is to use a multi-chip module (MCM) package technique to pack two power transistors into a single package. However, the MCM method incurs other side effects. Because the DMOS power transistor based on the BCD process or the like has the disadvantage of a low voltage limit, it is necessary to develop another circuit design with a high voltage limit while remaining in the state of a low inner resistance.